“Symmetric Large Size Unsigned Multiplication Using Embedded DSP Blocks in FPGAs”

Noureddine Chabini

Event Details
Wednesday, February 1, 2023
3:30 PM, 115 Avery Hall

4:30 PM, 115 Avery Hall

Noureddine Chabini, Ph.D.

Associate Professor, Royal Military College of Canada


Field Programmable Gate Arrays (FPGAs) are used in realizing real-life applications. The multiplication is a required arithmetic operation in many real-life applications. We report on synthesizing symmetric large size unsigned multiplication on Xilinx Virtex 6 FPGA family using embedded DSP blocks, which contain asymmetric 25x18 bits two’s complement embedded hardwired multipliers. We use published approaches for this synthesis and compare the results using the standard approach, which consists in synthesizing the VHDL operator *. Compared to the standard approach, the experimental results show that the clock period can be reduced at the price of increasing the area. We suggest future research directions.

Speaker Bio

Noureddine Chabini received the B.Sc. degree in Computer Science and Automatic Systems from Caddi Ayyad University, Marrakech, Morocco, in 1995, and the M.Sc. and Ph.D. degrees, in Computer Science, from the University of Montreal, Montreal, QC, Canada, in 1998 and 2001, respectively. He is currently an Associate Professor in the Department of Electrical and Computer Engineering at the Royal Military College of Canada, Kingston, ON, Canada. Before joining the Royal Military College of Canada in 2003, he was an Invited Researcher at Princeton University, Princeton, NJ, USA. Before joining Princeton University in 2002, he was an invited researcher at the École Polytechnique de Montréal, Montreal, QC, Canada. He has served as Associate Editor for the IEEE Canadian Journal of Electrical and Computer Engineering, and in the Technical Program Committees for various scientific conferences. His scientific research interests include: Algorithms for computer aided design of integrated digital systems; design for high performance; design for low power; arithmetic on FPGAs; compiler optimization techniques.