Challenges and Opportunities in Computing with NCFET

The inability of transistors to switch faster than 60mV/decade is one of the fundamental limits in physics for technology scaling, which had prevented the continuation of Dennard’s scaling more than a decade ago. As a result, on-chip power densities continuously increases with every new generation leading to excessive temperatures that seriously degrade the reliability of chips. In addition, technology scaling is reaching limits in which displacing few atoms within transistors, due to aging phenomena such Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), provokes uncertainty that may cause catastrophic errors during operation. Due to the inevitable need to include wider and wider timing guardbands towards sustaining reliability for the entire projected lifetime, the customary trend in which performance is gained with technology scaling becomes very difficult.

Negative-Capacitance Field-Effect Transistor (NCFET) is emerging as a promising new technology with various advantages as well as new challenges compared to conventional CMOS technology. NCFET technology can operate at lower voltage while they may still provide the same level of performance. While the exact trade-offs are still to be explored, it is obvious that lower power designs are possible. However, employing NCFET technology will have significant effect on circuits, architecture and system level management techniques. For example, as opposed to conventional CMOS technology, the power consumption: particularly the leakage current may have an inverse tendency as a function of the supply voltage. That means that conventional power management techniques for multi-core will not work any longer since they would lead to sub-optimal results depending on system-level workload properties. These are some examples of the implications at the architectural and system level that will be discussed during this talk after a short general introduction to the NCFET technology.