Ultra-Low Power Edge AI Devices in the IoT Context: The Quest for Brain Efficiency

David Atienza

Event Details
Wednesday, November 6, 2019
3:30 p.m., Avery 115

4:30 p.m., Avery 115

David Atienza

Associate Professor, Embedded Systems Laboratory, EPFL, Switzerland


Smart or edge AI devices are poised as the next frontier of innovation in the context of Internet-of-Things (IoT) to be able to provide personalized services, improve our quality of life and transform overall our society. This new family of smart edge devices provide a great opportunity for the next-generation of artificial intelligence (AI) based IoT services. However, major key challenges remain in achieving this potential due to inherent resource-constrained nature of IoT systems, coupled with their limited computing power and data gathering requirements for Big Data AI applications at the edge level, which can result in degraded and unreliable behavior and short lifetime. In this talk, Prof. Atienza will first discuss the challenges of ultra-low power (ULP) design and communication in smart edge AI devices for different applications using the specific context of Big Data healthcare. Then, the opportunities for edge computing and edge AI in next-generation smart IoT devices will be highlighted as a scalable way to fully deliver the concept of personalized medicine and home-user products. This new trend of smarter edge AI architectures will need to combine new ULP multi-core embedded systems with neural network accelerators, as well as including energy-scalable software layers to monitor different types of human and environmental signals using an event-driven monitoring approach. Overall, the next-generation of ULP edge AI devices will be able to gracefully adapt the energy consumption and precision of the service detection outputs according to the requirements of our surrounding world and available energy at each moment in time, as living organisms do to operate efficiently in the real world.

Speaker Bio

David Atienza is Associate Professor of Electrical and Computer Engineering and leads the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in Computer Science and Engineering from UCM (Spain) and IMEC (Belgium). His research interests focus on system-level design methodologies for energy-efficient multi-processor system-on-chip architectures (MPSoC) and next-generation smart embedded systems (particularly wearables) for the Internet of Things (IoT) era. In these fields, he is co-author of more than 300 publications, seven patents, and has received several best paper awards in top conferences. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. Dr. Atienza has received the DAC Under-40 Innovators Award in 2018, IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow, an ACM Distinguished Member, and the President (period 2018-2019) of IEEE CEDA.